Reliability properties in sub-50nm high performance high-k/metal gate stacks SiGe pMOSFETs

Author

Park, Min Sang ; Kang, Chang Yong ; Choi, Do-Young ; Sohn, Chang-Woo ; Jeong, Eui-Young ; Chung, Jinyong ; Lee, Jeong-Soo ; Jeong, Yoon-Ha

Author_Institution

Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea

fYear

2010

fDate

12-15 Oct. 2010

Firstpage

38

Lastpage

41

Abstract

We present the reliabilities in compressively strained SiGe channel pMOSFETs. A Si capping layer in SiGe channel pMOSFETs improved the negative bias temperature instability (NBTI) without device performance degradation. Also, the Si capped device exhibits the better NBTI reliability than the Si channel device. Because a Si capped structure forms the double barrier layer in the interface, it is the primary cause of improved NBTI. These results show that a Si capping layer should be used in SiGe channel pMOSFETs for better reliabilities and performance.

Keywords

Ge-Si alloys; MOSFET; elemental semiconductors; high-k dielectric thin films; semiconductor device reliability; silicon; NBTI reliability; SiGe-Si; capping layer; device performance degradation; double barrier layer; high-k-metal gate stack channel pMOSFET; negative bias temperature instability; reliability property; Logic gates; MOSFETs; Metals; Performance evaluation; Reliability; Silicon; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology Materials and Devices Conference (NMDC), 2010 IEEE

Conference_Location

Monterey, CA

Print_ISBN

978-1-4244-8896-4

Type

conf

DOI

10.1109/NMDC.2010.5651918

Filename

5651918