DocumentCode :
3341891
Title :
Single transistor learning synapse with long term storage
Author :
Hasler, Paul ; Diorio, Chris ; Minch, Bradley A. ; Mead, Carver
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Volume :
3
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
1660
Abstract :
We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectivity for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current
Keywords :
Hebbian learning; MOSFET; MOSFET circuits; backpropagation; hot carriers; neural chips; tunnelling; MOSIS process FET; backpropagation learning rule; column selectivity; electron tunneling; floating gate charge; hebbian learning rule; hot electron injection; input floating gate value product; long term storage; long term weight storage; row selectivity; single transistor learning synapse; single transistor synapse array; steady state source current; weight value update; Circuits; Computer hacking; Electrons; FETs; Fabrication; Implants; Read only memory; Silicon; Steady-state; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.523729
Filename :
523729
Link To Document :
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