Monotonicity constraints on path delays for efficient retiming with localized clock skew and variable register delay

Clock skew and delay characteristics associated with practical registers are significant factors affecting the retiming of synchronous circuits. Although work recently reported using branch and bound techniques offers a means for effective retiming taking these factors into account, the computational complexity involved is substantially greater than that associated with less general retiming algorithms that use standard linear programming methods. This paper presents sufficient conditions among values of localized clock skew and register characteristics which permit the retiming process to be achieved with a considerable reduction in computational complexity. The application of these conditions to some practical synchronous circuits is illustrated