DocumentCode
3343076
Title
A verification algorithm for logic circuits with internal variables
Author
Nakaoka, Toshihiro ; Wakabayashi, Shin´ichi ; Koide, Tetsushi ; Yoshida, Noriyoshi
Author_Institution
Fac. of Eng., Hiroshima Univ., Japan
Volume
3
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
1920
Abstract
In this paper, we present a formal verification method based on internal variables of a given circuit. In this method, the problem of deciding the logical equivalence of two logic circuits is transformed to the satisfiability problem, which is solved by constructing a set of BDDs, each of which is corresponding to an internal variable of the circuit. Experimental results showed the effectiveness of the proposed method
Keywords
Boolean functions; circuit CAD; combinational circuits; formal verification; integrated logic circuits; logic CAD; logic design; BDD; binary decision diagrams; formal verification method; internal variables; logic circuits; satisfiability problem; verification algorithm; Binary decision diagrams; Boolean functions; Circuit synthesis; Data structures; Formal verification; Input variables; Logic circuits; Partitioning algorithms; Telephony; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2570-2
Type
conf
DOI
10.1109/ISCAS.1995.523794
Filename
523794
Link To Document