Title :
Coverage of transistor-level and gate-level stuck-at-faults in CMOS checkers
Author :
Lidén, Peter ; Dahlgren, P.
Author_Institution :
Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
fDate :
30 Apr-3 May 1995
Abstract :
Transistor gate stuck-at and node stuck-at faults in self-testing checkers of various implementations are examined. Two types of CMOS implementations with different transistor driving strength ratios are considered. The coverage obtained for the classic gate-level stuck-at fault model for different test set sizes is compared with the corresponding coverage of transistor-level faults. It is shown that the coverage estimation using the gate-level stuck-at model is overly optimistic
Keywords :
CMOS logic circuits; VLSI; automatic testing; built-in self test; fault diagnosis; integrated circuit testing; logic testing; CMOS checkers; VLSI; coverage estimation; gate-level stuck-at-faults; node stuck-at faults; self-testing checkers; test set sizes; transistor driving strength ratios; transistor-level faults; Automatic testing; Built-in self-test; CMOS technology; Circuit faults; Circuit testing; Integrated circuit modeling; Runtime; Semiconductor device modeling; System testing; System-on-a-chip;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.523845
