Alternative architectures for the 2-D DCT algorithm

Recently, a new fast algorithm has been proposed for the computation of the 2-D N×N-point Discrete Cosine Transform, where N is decomposed into two mutually prime numbers N₁ and N₂. Using Prime-Factor Decomposition (PFD) and appropriate index mappings, the algorithm results in fewer multiplications than other fast 2-D DCT algorithms. In this paper, a methodology for systematic mapping of this algorithm onto hardware is presented. The proposed methodology reveals the existence of a few connected components in the signal-flow graph (SFG) of the algorithm and leads to architectures that can be systematically derived and exhibit varying throughput and hardware complexity