Analysis of the electrical and thermal properties of power DMOS devices during UIS supported by 2 - D process and device simulation

Analysis oj the electrical and thermal properties oj power DMOSFET devices based on the 2-D mixed mode modeling and simulation is presented. The physical behavior oj the device structure during undamped inductive switching (UlS) is studied on the multicel! structure with good and bad cells. The "bad" cell is dejined by the higher series resistance attached to the ptype well: The higher voltage drop on the bad cell turns the parasitic bipolar transistor on and large current starts to flow via bad cell. The generated heat and corresponding temperature growth opens the next parasitic bipolar transistor in the adjacent cell. Due to further inaease of current more heat is generated (a positive feedback). We observed that an increase of series resistance, e. g. due to fluctuations of contact resistance and specific resistance of frtype well could create such a weak spot in the device which jinalJy leads to the device failure.