Interconnect Challenges in a Many Core Compute Environment

It is already established that going forward, the roughly 2x/2yr performance improvements delivered over the last two decades will primarily come through parallelism rather than increasing clock frequencies due to associated power challenges. Provided software and tools continue to scale well with core and thread count, large core counts bring serious challenges both in the memory hierarchy and interconnect bandwidth both on-die, within the package, and off package. Simulations on anticipated future workloads help isolate where specific bottlenecks are likely to occur. New technologies both in die stacking and package- to-package interconnects will be required. These solutions will bring dramatic changes in the physical layer that may well break backward compatibility. Furthermore, these potential approaches are segment specific and involve complex tradeoffs of performance, cost, and power. This presentation will explore several approaches highlighting potential solutions and bandwidth requirements driven by likely future applications.