LcVc: Low-complexity vector-core for executing scalar/vector instructions

This paper proposes a low-complexity vector-core called LcVc for executing both scalar and vector instructions on the same execution datapath. A unified register file in the decode stage is used for storing both scalar operands and vector elements. The execution stage accepts a new set of operands each cycle and produces a new result. Rather than issuing vector instruction (1-D operations) as a whole, each vector operation is issued sequentially with the existing scalar issue hardware. All loads and stores of registers take place from the data cache in the memory access stage in a rate of one element per clock cycle. The hardware required to support the enhanced vector capability is insignificant (few incrementers and multiplexers), which results in reducing the area per core and increasing the number of cores available in a given chip area. Three key features distinguish LcVc architecture: a unified ISA to scalar and vector processing, low cost, and simplicity of organization. The use of LcVc approximately doubles the speedup of executing vector/matrix kernels such as vector addition, vector scaling, SAXPY, dot-product, matrix-vector multiplication, and matrix-matrix multiplication.