Wafer bonding and layer transfer processes for 4-junction high efficiency solar cells

A four-junction cell design consisting of InGaAs, InGaAsP, GaAs, and Ga_0.5In_0.5P subcells could reach 1×AM0 efficiencies of 35.4%, but relies on the integration of non-lattice-matched materials. Wafer bonding and layer transfer processes show promise in the fabrication of InP/Si epitaxial templates for growth of the bottom InGaAs and InGaAsP subcells on a Si support substrate. Subsequent wafer bonding and layer transfer of a thin Ge layer onto the lower subcell stack can serve as an epitaxial template for GaAs and Ga_0.5In_0.5P subcells. Present results indicate that optically active III/V compound semiconductors can be grown on both Ge/Si and InP/Si heterostructures. Current voltage electrical characterization of the interfaces of these structures indicates that both InP/Si and Ge/Si interfaces have specific resistances lower than 0.1 Ω cm² for heavily doped wafer bonded interfaces, enabling back surface power extraction from the finished cell structure.