150 μm Pitch Pb-Free Flipchip Packaging with Cu/Low-k Interconnects

This article focuses on the ILD layer structural stability including mechanical simulation with polymerencapsulation and redistribution process for 150um pitch Pb-free flipchip packaging of low-k/Cu interconnects. CVD (chemical vapor deposition) type low-k test vehicles with four Cu layers are fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution (RDL) technology are applied using wafer integration technology to minimize the stress from the solder bump pad to low-k ILD (inter layer dielectrics). The mechanical simulations are performed for RDL approach and normal direct bumping. According to the results with shear loading, RDL approach shows less stress than that of direct bumping at the solder joint. Simulation works show very promising results for vulnerable low-k devices. Two different interconnection schemes are studied and reported in the paper; i) Ti/NiV/Cu/Au UBM with Pb-free solder bumps and ii) copper post. For copper post interconnection, cost-effective and thick photoresist process is developed and optimized for electro Cu plating and solder is deposited on the top of Cu post. Bump shear test is carried out to evaluate the bump quality and failures are analyzed. In order to investigate UBM and solder joint reliability, multiple reflow tests are carried out. Microstructure observation and failure analysis are carried out and observed.