Configurable hardware implementation of triple-DES encryption algorithm for wireless local area network

This paper presents three implementations of triple data encryption standard (3DES) algorithm on a configurable platform. Implementations are aimed at the medium access control (MAC) protocol of a multimedia-capable wireless local area network (WLAN). For this reason, very strict timing constraints as well as demands for area-efficiency are present. The MAC processing is handled by a digital signal processor (DSP) and a Xilinx Virtex field programmable gate array (FPGA) chip. The latter one is also used for the presented encryption implementations. As a result of the study, 3DES implementations with small area and reasonable throughput and, on the contrary, with large area and very high throughput are realized. Even though 3DES turns out to be quite large and resource-demanding, the implementations still leave enough chip area for the other MAC functions. Consequently, the set requirements are met and the cipher can be integrated into the system