A low power reconfigurable DCT architecture to trade off image quality for computational complexity

Author

Park, Jongsun ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

Volume

5

fYear

2004

fDate

17-21 May 2004

Abstract

We present a low power reconfigurable DCT design, which achieves considerable computational complexity reduction in DCT operation with minimum image quality degradation. The approach is based on the modification of DCT bases in a bit-wise manner. Different computational complexity/image quality trade off levels are presented and a reconfigurable architecture. which can dynamically change from one trade off level to another, is also proposed. The reconfigurable DCT architecture can achieve power savings ranging from 20% to 70% for 5 different trade off levels.

Keywords

computational complexity; discrete cosine transforms; image coding; image reconstruction; low-power electronics; reconfigurable architectures; bit-wise DCT base modification; computational complexity/image quality trade off; image compression; low power DCT architecture; reconfigurable DCT architecture; reconstructed images; trade off levels; Computational complexity; Computer architecture; Degradation; Discrete cosine transforms; Frequency; Image coding; Image quality; Image reconstruction; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on

ISSN

1520-6149

Print_ISBN

0-7803-8484-9

Type

conf

DOI

10.1109/ICASSP.2004.1327036

Filename

1327036