Notice of RetractionDual image processing algorithms and parameter optimization

Notice of Retraction

After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.

We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.

The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.

Increasing calculation speed without affecting pixel calculation accuracy in fast image processing algorithms using parallel computation was always needed but controlled by Amdahl´s Law. In fact increasing number of processors uses same data bus reduces the speed and not allowing us to get the 20 times faster as we expected. As number of processors are limited due to sharing processors same data bus. Discussing in this paper dividing image frame into numbers of sections and discuss the ability to apply two different algorithms at the same time. Using same FPGA resources and keeping high accuracy and speed as a main target. Processors communication protocol traditionally depends upon main data bus to manage sending or receiving data each processor at a time. Our research in this paper avoided this traditional communication technique. It has been divided into 3 steps. First step was to use one image frame to be calculated on FPGA in a Data Flow computation technique and calculate the timing results and formulate the equation that govern it. Second step was making FPGA parallelization computation and also formulate its equation and verify it practically. Third step was to enhance the result of step 2 by making data overlap to over come the differences between divided image frame and a complete image frame calculation (Step 1) accuracy. Image frame were divided into 4 equal parts (64 row by 256 column) as mention in step 2. Image local operation algorithm is depending upon neighbor pixels. Edges accuracy in step 1 i- low only in the whole frame edges but in the step 2 we have it ar all 4 image parts edges. Overcoming this drawback was done by immersing overlap parallel calculations between the half of upper part of RAM and the half of the lower part (step 3). Comparing the data results from the whole image data and enhanced parallel data was made to ensure correct and same Gaussian output inside the Image frame, step 1&3. Formulating an equation for FPGA parallel- computing is very useful for performance evaluation and design time calculation as well as the advantage of not using data bus as a common data transfer. This parallel design gives the the advantage of applying different algorithms at each part of image frame.