Title :
Development of no flow underfill technology for next generation flip chip products
Author :
Pendse, Raj ; Choi, Y.N. ; Kim, K.M. ; Narvaez, Glenn ; Jafari, B. ; Singh, I.
Author_Institution :
STATSChipPAC Inc., Fremont, CA, USA
fDate :
31 May-3 June 2005
Abstract :
A no-flow underfill (NFU) process has been developed using a 11.5 × 11.5 mm graphics device in a 35 × 35 mm BGA package. Commonly known problems in NFU processing such as, "die floating" and "filler trapping" were resolved using a novel chip attach process involving controlled application of heat and pressure during chip placement. In addition, NFU materials with filler contents and distributions comparable to conventional capillary underfills were employed to ensure good long-term reliability of solder joints for large die sizes. Reliability testing showed two notable problem areas that had to be addressed by optimization of NFU material and assembly processes: (a) the formulation and content of flux in NFU had to be tailored to prevent onset of hydrolysis in the residual resin upon HAST or PCT exposure, which is typical in anhydride based resin formulations: (b) filler content in the 50 % range and good fillet coverage in the die corner regions was critical in achieving high temperature cycling reliability. The final optimized NFU formulation and process passed full qualifications for graphics devices. In this paper, the assembly process development, reliability testing and package optimization are covered in detail. Special emphasis is given to the understanding and resolution of reliability and failure modes unique to the NFU process. Benefits and challenges of future applications of NFU to hi Pb and Pb-free solder bumps is discussed.
Keywords :
ball grid arrays; circuit optimisation; filler metals; flip-chip devices; integrated circuit reliability; lead alloys; solders; BGA package; HAST exposure; NFU materials; NFU process; PCT exposure; Pb solder bump; Pb-free solder bump; anhydride based resin; assembly process; chip attach process; chip placement; cycling reliability; die floating; filler content; filler trapping; flip chip products; graphics device; no flow underfill technology; package optimization; reliability testing; residual resin; solder joints; Assembly; Flip chip; Graphics; Joining materials; Materials reliability; Packaging; Pressure control; Process control; Resins; Temperature control;
Conference_Titel :
Electronic Components and Technology Conference, 2005. Proceedings. 55th
Print_ISBN :
0-7803-8907-7
DOI :
10.1109/ECTC.2005.1441281