Logic synthesis of reconfigurable controllers

The paper presents a design methodology for reconfigurable, modular digital controller synthesis. It starts with behavioral specifications and goes through Register Transfer Level to rule-based logic expressions, rewritten in hardware description languages. The logic controller program can be initially specified as Petri net, IEC1131 Sequential Function Chart or UML state machine diagram. All considered graphical specifications are described in the one, unified, textual, rule-based format. After hierarchical encoding of concurrent states and super states, the diagrams can be directly mapped into the array of cells in a Field Programmable Gate Array (FPGA).