Flip chip assembly challenges using high density, thin core carriers

Electrical performance, signal density and fine core via manufacturing process constraints are driving a reduction in core thickness for flip chip carriers which target mid and high performance applications. While developing new flip chip carrier technologies to support these applications, focus on reliability performance was expected to dominate the development team´s work plan. Reliability performance of Endicott Interconnect Technologies´ new thin core carrier has proven to be very good and is not as sensitive to the assembly material, design and process variables which drives reliability performance of thicker core carriers. However, thin core carriers can show an increased sensitivity to variables which affect carrier and assembly level flatness. This has resulted in significant focus on the definition of flip chip assembly processes which maintain high yield and conformance to JEDEC component flatness requirements. This paper summarizes the learning and conclusions related to flip chip assembly of Endicott Interconnect Technologies´ CoreEASEI dense core carrier technology. The investigation focused on the impact of carrier attributes on carrier level flatness, the impact of underfill attributes on post underfill cure flatness, and the impact of lid attach attributes on post lid attach flatness.