Kirkendall voids at Cu/solder interface and their effects on solder joint reliability

Previous studies, especially papers by T-C. Chiu, K. Zeng, R. Stierman and D. Edwards, K. Ano (2004) and M. Date, T. Shoji, M. Fujiyoshi, K. Sato, and K.N. Tu (2004) ECTC conference, demonstrate extensive Kirkendall voids at the interface of solder joint to Cu substrate, and their significant effects on the impact and shock strength of the solder joints. This study focuses on two issues, the condition for the void formation, and effect of voids on solder joint reliability. Samples of electronic assemblies of different packages aged or thermal cycled were cross-sectioned by either FEB or sputtering etching. The results show that voids at Cu/solder interface formed extensively in some cases, but not so much in others. So far, we are not clear exactly what factors control the void formation; it seems that the Cu plating process and the small concentration of Ni in either solder or substrate influences the void density and distribution. Shock strength at 400G of BGA packages aged for 20 days at 125°C did not degrade; the failure occurred by either delamination at the fiber/resin interface underneath the non-solder mask defined Cu pads, or inside the solder where close to the solder mask defined Cu pads. We also curve-fitted the Chiu´s result of voids growth vs time at different temperatures with the equation of A = Ct ⁰⁵ exp (-Q/RT), to use it for prediction of the voided area at the product service condition.