Title :
An implementation of level-index arithmetic based on the low latency CORDIC system
Author :
Kwak, Jae-Hyuck ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
This paper presents a CORDIC-based implementation of level-index arithmetic. For obtaining fast operations as well as saving hardware complexity, we propose a combined processor architecture making use of the low latency CORDIC algorithms. The timing and area characteristics are compared with those obtained by previous approaches. The comparisons show that our implementation scheme needs less hardware than that required by the previous approaches, while the timing is comparable.
Keywords :
digital arithmetic; digital signal processing chips; timing; vector processor systems; area characteristics; combined processor architecture; fast operations; hardware complexity; level-index arithmetic; low latency CORDIC algorithms; low latency CORDIC system; timing characteristics; vectoring processor; Calculators; Computer architecture; Concurrent computing; Costs; Delay; Digital arithmetic; Equations; Hardware; Parallel processing; Timing;
Conference_Titel :
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5148-7
DOI :
10.1109/ACSSC.1998.750855
