A Simplified FPGA Implementation Based on an Improved DES Algorithm

Recently, DES has been the most widely used symmetric block cipher for information security. But many powerful attacks, such as differential attack and linear attack had been proposed for cryptanalyzing DES. This paper gives an introduction and theoretical analysis of DES Algorithm and proposes a new design of encryption key and S-box to improve the algorithm performance. The hardware language VHDL is used to design and implement of an improved simplified DES algorithm with improved security. The design expands the encryption key length, can resist linear cryptanalysis and ensure that there is not "trapdoor" in the password system.