Cached memory performance characterization of a wireless digital baseband processor

Author

Kannaw, S. ; Allen, Michael ; Fridman, Jose

Author_Institution

Analog Devices Inc, Austin, TX, USA

Volume

5

fYear

2004

fDate

17-21 May 2004

Abstract

We present performance analysis results of the MSP500 digital baseband (DBB) platform, a system developed at Analog Devices Inc., targeted at cellular handsets supporting the GSM, GPRS, and EDGE communication standards. We focus on a particular member of the MSP500 family, the AD6532 device, which integrates a Blackfin® core, and examine the execution time performance of a number of wireless physical layer software components from the perspective of an instruction- and data-cached memory hierarchy. The Blackfin is a 16-bit fixed-point core that combines some of the best features of DSPs and micro-controllers, and has support for a cached memory system.

Keywords

cache storage; cellular radio; digital radio; microprocessor chips; mobile handsets; packet radio networks; performance evaluation; signal processing; telecommunication computing; AD6532; Analog Devices MSP500 digital baseband platform; Blackfin; DSP; EDGE; GPRS; GSM; cached memory performance; cellular handsets; communications software; data-cached memory hierarchy; instruction-cached memory hierarchy; micro-controllers; wireless digital baseband processor; wireless physical layer software components; Baseband; Communication standards; Digital signal processing; GSM; Ground penetrating radar; IEEE members; Performance analysis; Random access memory; Software standards; Telephone sets;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on

ISSN

1520-6149

Print_ISBN

0-7803-8484-9

Type

conf

DOI

10.1109/ICASSP.2004.1327122

Filename

1327122