DocumentCode :
3347243
Title :
Drop test reliability of wafer level chip scale packages
Author :
Alajoki, Mikko ; Nguyen, Luu ; Kivilahti, Jorma
Author_Institution :
Lab. of Electron. Production Technol., Helsinki Univ. of Technol., Espoo, Finland
fYear :
2005
fDate :
31 May-3 June 2005
Firstpage :
637
Abstract :
The reliability of the two different types of WL-CSP components being reflow-soldered with a near eutectic Sn3.8Ag0.7Cu and eutectic SnPb solder pastes on Ni(P)/Au-and OSP-coated multilayer printed wiring boards have been investigated by employing the standard drop test, statistical failure analyses, fractography and microstructural characterization methods. A significant difference in the reliability performance of the components was observed: the components with the (Al)Ni(V)/Cu metallization (UBM) were more reliable than those with the electroless Ni(P)/Au metallization ndependently of the bump, solder paste, surface finish materials or the pad structure of the boards used. The failure analyses revealed that the primary failure mode in the component side is the cracking of interconnections along a brittle NiSnP layer between the electroless Ni(P) of high P-content and the solder alloy, while components with (Al)Ni(V)/Cu UBM fail by cracking along the [Cu,Ni]6Sn5 intermetallic layer. On the board side the cracking occurs in the porous NiSnP layer formed between the electroless Ni(P) metallization and the (Cu,Ni)6Sn5 intermetallic layer. The fact that the cracking occurs predominantly at the components side reaction layer is due to three factors: higher normal stresses in the component side, brittleness of the reaction layer(s) and the strain-rate hardening of the bulk solder interconnections. It is to be noted that the primary failure mode differs from that typically observed in thermally cycled test assemblies, where the nucleation and propagation of cracks are strongly enhanced by the recrystallization of the solder interconnections.
Keywords :
brittle fracture; chip scale packaging; failure analysis; fractography; impact testing; integrated circuit reliability; printed circuits; reflow soldering; solders; drop test reliability; eutectic solder; fractography; intermetallic layer; metallization; microstructural characterization; multilayer printed wiring boards; reflow soldering; solder interconnections; statistical failure analyses; strain rate hardening; wafer level chip scale packages; Chip scale packaging; Failure analysis; Gold; Intermetallic; Materials reliability; Metallization; Nonhomogeneous media; Testing; Wafer scale integration; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2005. Proceedings. 55th
ISSN :
0569-5503
Print_ISBN :
0-7803-8907-7
Type :
conf
DOI :
10.1109/ECTC.2005.1441336
Filename :
1441336
Link To Document :
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