• DocumentCode
    3347298
  • Title

    Wafer level package solder joint reliability study for portable electronic devices

  • Author

    Jang, Se-Young ; Park, Tae-Sang ; Kim, Yeon-Sung ; Jeong, Jae-Woo ; Jung-Je Ban ; Kang, Dong-Ki

  • Author_Institution
    Inst. of Mechatronics, Samsung Electron. Co. Ltd., Suwon, South Korea
  • fYear
    2005
  • fDate
    31 May-3 June 2005
  • Firstpage
    660
  • Abstract
    Small form factor WLP (or WLCSP) type component has been increasingly applied to portable electronic devices. However, wafer level package type active components are more vulnerable to the failure than the passive or conventional BGA or QFP type active components. WLP constitute a neck point in terms of PCB assembly reliability. Therefore, it is very important to optimize the structure and material to secure high reliability of PCB assembly. Three variables are chosen for WLP reliability evaluation. They are solder ball size, PCB pad size, and underfill (use or non-use). DOE (design of experiment) technique is adopted to analyze variables effects on WLP solder joint lifetime. Board assembly level thermal cycling, high temperature and high humidity, and 4-point bending tests are employed as output parameters. The TC test results are compared with the finite element analysis. Solder joint cracks were mainly initiated from the triple point in IC side where solder, redistribution layer, and UBM meet together. WLP ball size was the major factor to determine solder joint lifetime whereas PCB pad size was not a critical parameter in all three reliability tests. Ironically, for the small ball sized WLPs, underfill decreased thermal fatigue lifetime. This is quite a different result compared with other previous reports. This discrepancy is presumably due to improper combination of underfill material property with high stress induced WLP passivation material, BCB (Benzocyclobuten).
  • Keywords
    ball grid arrays; chip scale packaging; consumer electronics; design of experiments; reliability; solders; thermal stress cracking; PCB assembly reliability; PCB pad size; design of experiment; portable electronic devices; solder ball size; solder joint lifetime; solder joint reliability; structure optimisation; thermal fatigue lifetime; underfill; wafer level package; Assembly; Electronics packaging; Humidity; Materials reliability; Neck; Soldering; Temperature; Testing; US Department of Energy; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2005. Proceedings. 55th
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-8907-7
  • Type

    conf

  • DOI
    10.1109/ECTC.2005.1441339
  • Filename
    1441339