• DocumentCode
    3348057
  • Title

    A fully asynchronous superscalar architecture

  • Author

    Arvind, D.K. ; Mullins, Robert D.

  • Author_Institution
    Div. of Inf., Edinburgh Univ., UK
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    17
  • Lastpage
    22
  • Abstract
    An asynchronous superscalar architecture is presented based on a novel architectural feature called instruction compounding. This enables efficient dynamic scheduling and forwarding of data based on local information, while maintaining the advantages of asynchrony in terms of exploiting actual delays. Results are presented in which statically and dynamically compounded architectures are compared against an equivalent synchronous superscalar architecture
  • Keywords
    parallel architectures; processor scheduling; data forwarding; delays; dynamically compounded architectures; efficient dynamic scheduling; fully asynchronous superscalar architecture; instruction compounding; local information; statically compounded architectures; Asynchronous circuits; Clocks; Electromagnetic interference; Frequency; Informatics; Logic; Pipelines; Power dissipation; Signal design; Signal processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures and Compilation Techniques, 1999. Proceedings. 1999 International Conference on
  • Conference_Location
    Newport Beach, CA
  • ISSN
    1089-795X
  • Print_ISBN
    0-7695-0425-6
  • Type

    conf

  • DOI
    10.1109/PACT.1999.807401
  • Filename
    807401
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3348057