Title :
Model of Source Code Analyzer for Hardware Description Languages
Author :
Melnyk, Dmytro ; Zaychenko, Sergiy ; Kolesnikov, Kostyantyn ; Lukashenko, Olga
Author_Institution :
Design Autom. Dept., Kharkov Nat. Univ. of Radioelectron., Kharkov
Abstract :
Model of system that detects common designer errors at the design entry stage. System is based on programmable rules and can be used in pair with any modern HDL compiler.
Keywords :
hardware description languages; integrated circuit design; program compilers; HDL compiler; designer errors; hardware description languages; programmable rules; source code analyzer; Costs; Design automation; Displays; Electronic mail; Engines; Hardware design languages; Job design; Libraries; Productivity; Program processors; Checker; Compiler; Elaborator; Hardware Description Language; Lint; Rule;
Conference_Titel :
CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of
Conference_Location :
Lviv-Polyana
Print_ISBN :
966-533-587-0
DOI :
10.1109/CADSM.2007.4297495
