Memory architecture support for the SIMD construction of a Gaussian pyramid

A memory system is introduced for the efficient construction of a Gaussian pyramid. The memory system consists of an address calculating circuit, an address routing circuit, a data routing circuit, a memory module selection circuit, and 2ⁿ+1 memory modules. The memory system provides parallel access to 2ⁿ image points whose patterns are a block, a row, or a column, where the interval of the block or column is one and the interval of the row is one or two. The performance of a generic SIMD (single-instruction multiple-data) processor using the proposed memory system is compared with that of one using an interleaved memory system for the recursive construction of a Gaussian pyramid