Author_Institution :
Dept. of Mech. Eng., Chang Gung Univ., Tao-Yuan, Taiwan
Abstract :
The purposes of this study are two folds: one is to attempt to develop a new, suitable test method for differentiating the factors that affect the variability of die strength, and the other is to investigate the failure and fatigue strength of silicon dies. In this study, a new test method, a plate-on-elastic-foundation test (PEFT) associated with point-or line-loading has been proposed and evaluated. It is found that the PEFT can provide not only a simple, chipping-free test for dummy or real IC chips without limitation of size, but also a stress field similar to the temperature loading. The test data obtained from the current test are presented for those failed on IC and ground surfaces in real IC chips. It is found that the good consistency of the die strength data with minor scatter from both the point- and line-load tests for the specimens failed on IC surfaces, but not for the ones failed on the ground surfaces. The reason for this is that the inconsistency of strength data from both tests for failure on ground surfaces is due to edge chipping involved, and the larger scatter is resulted from the combined factors of the angle of grinding marks, planes of weakness of material, and loading stress state. The surface roughness of the dies measured by atomic force microscopy is correlated with the failure mode and strength from the tests. It is found that the silicon die strength is dominated by the roughness on failure surface, and their failure modes always appear along the parallel and normal to the edges of the die, which might be the weak plane of the crystal lattice of silicon. The specimens with artificial cracks have been further tested. It has been proved that the die strength dominated by the crack initiation depends on the most severe defect and its failure mode is controlled by a special weak plane after the crack initiation. This study concludes that there are four factors to influence die strength: the surface conditions of the die (including grinding-line direction and surface roughness), the edge crack of the die (so-called edge chipping created during the cutting process), the weak planes of the crystal lattice of silicon, and, sometimes, the cause from different loading types. The fatigue strength of the dies is also determined to be about - 25% lower than static one.
Keywords :
cracks; electronics packaging; failure analysis; fatigue testing; mechanical strength; mechanical testing; surface roughness; Si; edge chipping; edge cracks; failure mode; failure strength; fatigue strength; grinding marks; grinding-line direction; line loading; loading stress state; plate-on-elastic-foundation test; point loading; silicon die strength; surface conditions; surface roughness; test method; weakness plane; Atomic measurements; Fatigue; Force measurement; Integrated circuit testing; Rough surfaces; Scattering; Silicon; Stress; Surface cracks; Surface roughness;