An exact hardware implementation of the Boltzmann machine

The author presents a faithful hardware implementation (built on the top of DECPeRLe-1, a reconfigurable coprocessor closely coupled with its host machine, a DECstation 500) of the Boltzmann machine. The prototype performs 505 megasynapses (million of additions and multiplications) per second, using 16-b fixed-point weights. It can emulate fully connected instances of the Boltzmann machine containing up to 1438 variables. This specialized hardware only executes the simplest part of the Boltzmann machine algorithm, namely, multiplying matrices of numbers by vectors of bits. The other operations (which are complicated, but only require a modest amount of computation) are performed by the host processor. It is noted that the key point of this work resides in establishing the right design choices. Among these, the most important ones are the rejection of ´neural parallelism´, which makes the implementation exact, and the algorithm used to generate random numbers in software, which allows the hardware to be simple. The fact that DECPeRLe-1 makes hardware development cheap and fast was essential in this work