SMALL: a scalable multithreaded architecture to exploit large locality

The authors propose a multithreaded architecture that performs synchronization efficiently by following a layered approach, exploits larger locality by using large, resident activations, and reduces the number of load stalls with the help of a novel high-speed buffer organization. The performance of the proposed architecture is evaluated using deterministic discrete-event simulation. Initial simulation results indicate that the architecture can achieve high performance in terms of both speedup and processor utilization