Title :
Fault Coverage Improving Based on Testability Analysis of the VHDL Code
Author :
Kaminska, Maryna ; Hahanov, Vladimir ; Hahanova, Anna ; Parfentiy, Alexander
Author_Institution :
DAD Dept., Kharkov Nat. Univ. of Radio Electron., Kharkov
Abstract :
Method of digital device testability analysis, which represented on the system level (VHDL description) as oriented graph for verification and test synthesis tasks simplification for fault coverage improving on the given test patterns is offered. Method is based on the topological analysis of oriented graph and his further modification by separation of testing and functional procedures for testability improving and testing procedure simplification.
Keywords :
boundary scan testing; circuit testing; design for testability; fault diagnosis; hardware description languages; VHDL code description; boundary scan technology; digital circuit model description; digital device testability analysis; fault coverage method; Circuit faults; Circuit testing; Controllability; Hardware design languages; Logic circuits; Logic devices; Logic testing; Observability; Pattern analysis; System testing; Verification; boundary scan technology; controllability; observability; testability;
Conference_Titel :
CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of
Conference_Location :
Lviv-Polyana
Print_ISBN :
966-533-587-0
DOI :
10.1109/CADSM.2007.4297578
