A Light-weighted Viterbi Decoder Implemented by FPGA

In this paper, a light-weighted pipelined serial Viterbi Decoder is implemented for resource saving purpose. The trace back module of the decoder consumes fewer logical resources by employing a RAM-based Register Exchange architecture. All the metric and trace back bits are stored in the RAM to save logical resources. Synthesis results show that, the proposed architecture can save more than half of resource utilization than fabric IP core and has the minimum logic consumption than almost other schemes we can find with nearly no performance loss.