Title :
Evaluation of a technology for a synchronous application
Author_Institution :
Hitachi America Ltd., Brisbane, CA
Abstract :
A method is discussed describing an initial `first pass´ performance evaluation on how well a technology will fit into a system design. The method involves calculating, from the vendor specifications, maximum chip to chip interconnect toggling frequency and internal to the chip, the maximum number of gates that can be inserted in between two latches clocked by the same clock. This method is meant to allow a fast way to compare technologies and should be only taken as a portion of an overall evaluation
Keywords :
logic design; sequential circuits; chip to chip interconnect toggling frequency; synchronous application; vendor specifications; Artificial intelligence; Clocks; Delay effects; Frequency; Isolation technology; Project management; System performance; System-on-a-chip; Technology management; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242847
