Title :
Circuit design for full scan ATPG
Author :
Faris, Stephen J.
Author_Institution :
Texas Instrum. Inc., Waltham, MA, USA
Abstract :
The author discusses full scan ATPG (automatic test pattern generation) ASIC designs. He examines the edge scan and LSSD (level sensitive scan design) versus nonscan designs in terms of gate overhead, power dissipation and cycle time for typical ASIC processes. In addition, problems and solutions to full scan design issues such as clocking schemes, asynchronous logic, latches and nonscan blocks are described
Keywords :
application specific integrated circuits; automatic testing; design for testability; integrated circuit testing; integrated logic circuits; logic design; logic testing; ASIC designs; LSSD; asynchronous logic; automatic test pattern generation; clocking schemes; cycle time; edge scan; full scan ATPG; gate overhead; latches; level sensitive scan design; nonscan blocks; nonscan designs; power dissipation; Application specific integrated circuits; Automatic test pattern generation; Circuit synthesis; Circuit testing; Clocks; Latches; Logic design; Master-slave; Shift registers; Test pattern generators;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242850
