A testable model for stoppable clock ASICS

Author

Traver, Cherrice Ann

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38412

Abstract

A testable model for globally asynchronous ASICs is presented. These circuits operate without a global clock and are useful for pipelined or data-driven architectures. The ASIC can be partitioned into several locally clocked modules and control is distributed throughout these modules. A test methodology is presented which partitions each locally clocked module into synchronous and asynchronous components in test mode. Design for testability techniques are used to further simplify the testing process

Keywords

application specific integrated circuits; asynchronous sequential logic; clocks; design for testability; integrated circuit testing; integrated logic circuits; logic design; logic testing; timing circuits; asynchronous components; data-driven architectures; globally asynchronous ASICs; locally clocked modules; pipelined architecture; stoppable clock ASICS; synchronous components; test methodology; testable model; Application specific integrated circuits; Circuit testing; Clocks; Costs; Design for testability; Distributed control; Hazards; Logic design; Protocols; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242853

Filename

242853