Title :
Ground bounce and reduction techniques [CMOS VLSI]
Author_Institution :
AT&T Bell Labs., Allentown, PA, USA
Abstract :
VLSI has progressed to reduce the minimum design feature and reduce delay. However, when CMOS circuits rapidly charge or discharge large capacitive loads simultaneously, the corresponding current through the parasitic inductance of the bonding and package lead wiring connecting the chip to one of the power supplies (VDD or VSS) causes a voltage drop to occur. This variation in voltage at the VDD or VSS node with respect to an external ground is called ground bounce. As VLSI improves performance by decreasing delay, ground bounce generation becomes a more serious problem for digital and mixed signal chip designs. The author discusses techniques to reduce ground bounce. One method is to automatically compensate for the normal processing variation´s effect on delay and ground bounce. Another is to utilize substrate conduction to reduce the external parasitic inductance
Keywords :
CMOS integrated circuits; VLSI; digital integrated circuits; integrated circuit technology; mixed analogue-digital integrated circuits; CMOS circuits; VLSI; bounce reduction; capacitive loads; external parasitic inductance; ground bounce; mixed signal chip designs; substrate conduction; voltage drop; Bonding; CMOS technology; Circuits; Delay; Inductance; Packaging; Variable structure systems; Very large scale integration; Voltage; Wiring;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242865