DocumentCode :
3349949
Title :
An ASIC CAM design for associative set processors
Author :
Correa, Nelson ; Garcia, Alvaro ; Duarte, M.C. ; Gonzalez, Fernel
Author_Institution :
Dept. of Electr. Eng., Univ. de Los Andes, Begota, Colombia
fYear :
1991
fDate :
23-27 Sep 1991
Lastpage :
38047
Abstract :
One of the key requirements in systems for symbolic computation is the fast and efficient execution of set operations, such as addition, removal, or test for membership of an element in a given set S. Content-addressable memory (CAM) offers the potential for massive fine-grained parallelism in the implementation of these operations, yielding a potential speedup of O(l Sl). The authors describes an ASIC design of a 32×32 CMOS static CAM for use in an associative set processor
Keywords :
CMOS integrated circuits; application specific integrated circuits; content-addressable storage; integrated memory circuits; ASIC CAM design; CMOS static CAM; associative set processors; massive fine-grained parallelism; Application specific integrated circuits; Bandwidth; CADCAM; Computer aided instruction; Computer aided manufacturing; Parallel processing; Random access memory; Registers; Relational databases; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
Type :
conf
DOI :
10.1109/ASIC.1991.242871
Filename :
242871
Link To Document :
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