DocumentCode :
3350127
Title :
Impact of ESD-induced soft drain junction damage on CMOS product lifetime
Author :
Reiner, Joachim C. ; Keller, Thomas ; Jäggi, Hans ; Mira, Silvio
Author_Institution :
Philip Semicond. AG, Zurich, Switzerland
fYear :
2001
fDate :
2001
Firstpage :
77
Lastpage :
78
Abstract :
The impact of ESD-induced soft drain junction damage on product lifetime was investigated. Several thousand input-output (I/O) pads of a 0.35 μm CMOS IC were stressed by ESD (electrostatic discharge) and subsequently subjected to bakes, ESD re-stress and high temperature operating life tests. While the ESD-induced soft drain junction damage appears to be stable versus temperature stress and ESD re-stress, it results in early failures during accelerated operating life tests. These life test failures are caused by breakdown of the gate oxide which was left unbroken during the ESD stress that caused the ESD-induced soft drain junction damage. Thus, ESD-induced soft drain junction damage might cause a reliability risk (latent ESD failure). Consequently, it needs to be avoided by assuring sufficient robustness of the IC against this ESD damage mechanism. A leakage current criterion of 1 μA is rather large to detect this kind of damage after ESD stress
Keywords :
CMOS integrated circuits; electric breakdown; electrostatic discharge; integrated circuit reliability; integrated circuit testing; leakage currents; life testing; thermal stresses; 0.35 micron; 1 muA; CMOS IC; CMOS product lifetime; ESD; ESD damage mechanism; ESD re-stress; ESD stress; ESD-induced soft drain junction damage; IC robustness; accelerated operating life tests; bakes; early failures; electrostatic discharge; gate oxide breakdown; high temperature operating life tests; input-output pads; latent ESD failure; leakage current criterion; life test failures; product lifetime; reliability risk; temperature stress; CMOS integrated circuits; Electric breakdown; Electrostatic discharge; Integrated circuit testing; Leakage current; Life estimation; Life testing; Robustness; Stress; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium on the
Print_ISBN :
0-7803-6675-1
Type :
conf
DOI :
10.1109/IPFA.2001.941459
Filename :
941459
Link To Document :
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