Title :
On clock routing for general cell layouts
Author :
Cong, Jason ; Kahng, Andrew ; Robins, Gabriel
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
Addresses the minimum-skew clock routing problem in general cell designs. The authors present a bottom-up construction method for clock distribution trees based on a generalized matching computation in channel intersection graphs. The clock routing trees produced by their method attain almost zero skew with only modest wirelength penalty. Experimental results show that clock skew of their routing tree is no more than 2% of that of a minimum spanning tree, while on average the cost of the tree is only 50% more than that of a minimum spanning tree
Keywords :
VLSI; application specific integrated circuits; circuit layout CAD; clocks; digital integrated circuits; minimisation; network routing; VLSI; bottom-up construction method; channel intersection graphs; clock distribution trees; clock routing trees; clock skew minimisation; general cell designs; general cell layouts; generalized matching computation; minimum-skew clock routing problem; synchronous logic; wirelength penalty; Circuits; Clocks; Computer science; Costs; Delay; Partitioning algorithms; Routing; Synchronization; Very large scale integration; Wire;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242894
