DocumentCode
3350343
Title
Routability design for sea-of-cells
Author
Xiong, Xiao-Ming
Author_Institution
Applied Micro Circuits Corp., San Diego, CA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38047
Abstract
The routability design of a core cell for three layer sea-of-cells is discussed. A formula to estimate both horizontal and vertical routing tracks in a core cell is derived. The estimation is based on average pin counts per base cell, and the number of rows and columns of base cells in an array. The formula has been applied to a series of bipolar and BiCMOS array families. The accuracy of the prediction has been verified by both experiments and actual chip production
Keywords
VLSI; application specific integrated circuits; circuit layout CAD; logic arrays; network routing; BiCMOS array families; actual chip production; average pin counts; bipolar array families; core cell; gate arrays; horizontal routing tracks; number of rows; routability design; routability design approach; routing tracks estimation; sea of gates; sea-of-cells; semicustom design; three layer sea-of-cells; vertical routing tracks; Accuracy; Design methodology; Integrated circuit interconnections; Manufacturing; Pins; Production; Routing; Silicon; Telephony; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242896
Filename
242896
Link To Document