Analysis of Harmonic Environment for Assembling Capacitors and Validation on RTDS Simulator

Instead of ordinary shunt capacitor banks, assembling capacitor are more extensively used in power system for voltage support and power factor correction due to its larger reactive power compensation per bank as well as free-maintenance. However, just owing to large capacitance and special internal configuration, it may aggravate system issue of harmonic amplification and thus may contrarily further aggravate itself and trigger it failure. This paper presents the analysis for assembling capacitor operation environment via a typical substation model and the validation on real time digital simulator (RTDS). The maximum capacitance error limit between phase and phase and the various series inductances in capacitor are considered to discuss the harmonic level endured by the equipment. The regulation limits for total harmonic distortion (THD) and imbalance feeder voltage in substation are also taken into account. As a result, a method with math equations is given for estimating the severity of harmonic pollution and the possibility of equipment damage.