Title :
Incremental timing optimization during multiple stages of logic synthesis
Author :
Nishio, Seiichi ; Kitahara, Takeshi ; Sekine, Masatoshi
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
An effective approach for timing optimization in a logic synthesis system is presented. One of the main features of the approach is that it attempts to optimize timing at three stages of circuit abstraction. The effectiveness and limitations of this method at the stage of technology independent gate level are identified through experiments
Keywords :
VLSI; integrated logic circuits; logic CAD; effectiveness; experiments; limitations; logic synthesis system; speed-up transformations; stages of circuit abstraction; stages of logic synthesis; technology independent gate level; timing optimization; Circuit synthesis; Control system synthesis; Delay estimation; Libraries; Logic arrays; Logic circuits; Logic design; Network synthesis; Timing; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242903
