DocumentCode
3350625
Title
Testing of imbedded memories in ASICs
Author
Mulherkar, Shashi
Author_Institution
Northern Telecom Ltd., Brampton, Ont., Canada
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38047
Abstract
The testing of imbedded memories in ASICs is becoming increasingly difficult due to the large size of memories which ASIC vendors offer. This paper illustrates an algorithm which was developed and successfully implemented on the LTX Trillium Micromaster tester
Keywords
SRAM chips; application specific integrated circuits; circuit analysis computing; integrated circuit testing; logic testing; ASICs; LTX Trillium Micromaster tester; SRAM; algorithm; imbedded memories; testing; Algorithms; Amplitude shift keying; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Intelligent networks; Random access memory; Registers; Telecommunications;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242913
Filename
242913
Link To Document