DocumentCode
3350650
Title
Toshiba IEEE 1149.1 (JTAG) development summary
Author
Thomas, John
Author_Institution
Toshiba America Electronic Components Inc., Sunnyvale, CA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
37987
Abstract
TAEC has developed a simple and versatile IEEE 1149.1 (JTAG) sub-system methodology for high performance gate array ASICs based on a modular scheme with sub-nanosecond propagation delay penalties for CMOS I/O voltage levels. The scheme uses 14 different macrofunctions which can be combined to form a variety of JTAG sub-systems
Keywords
CMOS integrated circuits; application specific integrated circuits; boundary scan testing; integrated circuit testing; logic arrays; logic testing; CMOS I/O voltage levels; IEEE 1149.1 subsystem methodology; JTAG architecture; Toshiba; gate array ASICs; modular scheme; propagation delay penalties; soft macrofunctions; Application specific integrated circuits; CMOS technology; Circuit testing; Clocks; Electronic components; Instruction sets; Macrocell networks; Pins; Propagation delay; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242915
Filename
242915
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