DocumentCode
3350665
Title
A BiCMOS tristate buffer for high-speed microprocessor VLSI
Author
Kuo, J.B. ; Liao, H.J.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38108
Abstract
This paper presents a high speed BiCMOS tristate buffer with a single bipolar device pull-up structure for driving a bus with a large capacitive load. With the new pull-structure, the BiCMOS tristate buffer, which is suitable for microprocessor VLSI, has an improvement in delay time of 30% compared with the standard BiCMOS tristate buffer
Keywords
BiCMOS integrated circuits; VLSI; application specific integrated circuits; buffer circuits; integrated logic circuits; microprocessor chips; BiCMOS tristate buffer; data bus drive; delay time; high-speed microprocessor VLSI; single bipolar device pull-up structure; BiCMOS integrated circuits; Bipolar transistors; CMOS logic circuits; Delay effects; Logic circuits; Logic devices; Logic gates; MOS devices; Microprocessors; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242916
Filename
242916
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