DocumentCode
3350739
Title
A 0.8 μm 29000 gate BICMOS-ECL mixed array with 40 kb/5 ns embedded SRAM
Author
Yung, Y.S. ; Sinh, N. ; Tseng, C. ; Ho, L. ; Truong, M. ; Yee, L. ; Lam, N.C.
Author_Institution
ASIC Div., National Semiconductor Corp., Santa Clara, CA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38169
Abstract
Using National Semiconductor´s ABiC IV technology, a 0.8 μm single poly advanced BiCMOS process, a high performance mixed BiCMOS-ECL array with 5 ns access time embedded SRAM is achieved. The array integrates 105000 ECL gates, 18690 BiCMOS gates, and 40 kbits of BiCMOS SRAM on the same chip. I/O interface can be ECL, TTL, CMOS or mixed
Keywords
BiCMOS integrated circuits; SRAM chips; VLSI; application specific integrated circuits; emitter-coupled logic; logic arrays; 0.8 micron; 40 kbit; 5 ns; ABiC IV technology; BiCMOS SRAM; BiCMOS gates; CMOS I/O; ECL I/O; ECL gates; I/O interface; National Semiconductor; TTL I/O; VLSI; access time; ceramic PGA package; embedded SRAM; mixed BiCMOS-ECL array; polycrystalline Si; single poly advanced BiCMOS process; Application software; BiCMOS integrated circuits; Bonding; Computer applications; Embedded computing; High performance computing; Packaging machines; Power dissipation; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242922
Filename
242922
Link To Document