A sub-micron ECL gate array family

Author

Truong, Mau ; Yee, L. ; Sinh, N. ; Ho, C.W. ; Lalchandani, A. ; Lam, N.C.

Author_Institution

ASIC Div., National Semiconductor Corp., Santa Clara, CA, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38108

Abstract

A new ECL gate array family was developed with 50ps typical gate delay under 1 mA switching current. It pushes the gate count to over 100K gates with 320 I/O signal pads. The process used is National Semiconductor´s fourth generation, 0.8 μm ASPECT III process. A frequency divider test with 0.6mA switching current was used to prove the input frequency exceeds 2.5 GHz for the first time utilizing silicon technology. With interconnect delay at 1 ps/mil, this ECL gate array family is optimized for VLSI designs

Keywords

VLSI; application specific integrated circuits; bipolar integrated circuits; emitter-coupled logic; logic arrays; 0.6 to 1 mA; 0.8 micron; 2.5 GHz; 50 ps; ASIC; ASPECT III process; ECL gate array family; I/O 320 pads; National Semiconductor; Si technology; VLSI designs; frequency divider; gate count; gate delay; input frequency; interconnect delay; submicron; switching current; Application specific integrated circuits; Delay; Design optimization; Frequency conversion; Logic functions; Routing; Silicides; Silicon; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242924

Filename

242924