Title :
Performance evaluation of cascadable built-in tester for large I/O multichip modules
Author :
Lin, Ting-Ting Y. ; Kaseff, Charles
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
A cascadable built-in tester (CBIT) for testing multichip modules (MCMs) with large number of I/O pins is introduced. The CBIT can function both as a test pattern generator and as a signature analyzer. CBITs are cascadable to produce a maximal length pseudo-random sequence. This sequence yields high fault coverage due to the small signature aliasing probability and the uniqueness of the test patterns generated. A `pipelined test´ concept is applied, which concurrently shares CBITs between multiple MCMs to reduce overall test time and area overhead
Keywords :
built-in self test; integrated circuit testing; logic testing; multichip modules; packaging; CBIT; MCM; area overhead; cascadable built-in tester; fault coverage; large I/O multichip modules; large number of I/O pins; maximal length pseudo-random sequence; multiple MCMs; overall test time; performance evaluation; pipelined test; signature analyzer; small signature aliasing probability; test pattern generator; Built-in self-test; Circuit faults; Circuit testing; Design methodology; Logic design; Multichip modules; Packaging; Pipelines; System testing; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242926
