Performance evaluation of cascadable built-in tester for large I/O multichip modules

A cascadable built-in tester (CBIT) for testing multichip modules (MCMs) with large number of I/O pins is introduced. The CBIT can function both as a test pattern generator and as a signature analyzer. CBITs are cascadable to produce a maximal length pseudo-random sequence. This sequence yields high fault coverage due to the small signature aliasing probability and the uniqueness of the test patterns generated. A `pipelined test´ concept is applied, which concurrently shares CBITs between multiple MCMs to reduce overall test time and area overhead