Multiple mixed-level HDL generation from schematics for ASIC design

Presents the development of an ASIC CAE tool which automatically generates the multiple mixed-level hardware description language (VHDL/Verilog) from the schematic capture system. In order to support the multi-level design abstraction, the schematic capture system in this paper is extended to accept both the schematic drawings and the text as an input. The graphical and textual inputs are mixed within the schematics to generate the mixed-level VHDL/Verilog output code. An intermediate data structure based on the abstract syntax tree has been defined and used during the generation process. The data structure provides a great deal of flexibility. The tool helps ASIC designer to capture any level of design abstraction by using the schematic capture system which he/she is familiar with