ASIC design system for radiation environments

Author

Braatz, James C. ; White, Michael L.

Author_Institution

Div. of Electron. Syst., Boeing Aerospace & Electronics, Seattle, WA, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38078

Abstract

A complete radiation hardened ASIC design system, under development by a three company team is described. The compiler approach design system, with radiation hardness tunable library cells, allows the designer to concentrate on the circuit design rather than the details of hardness affecting geometry layout. The designer must be aware of the hardness requirements and the limitations of the available compilable process technologies, but is not burdened with the transistor level design techniques to achieve the hardness desired

Keywords

application specific integrated circuits; circuit layout CAD; digital integrated circuits; radiation hardening (electronics); ASIC design system; circuit design; compiler approach design system; geometry layout; hardness requirements; limitations; radiation environments; radiation hardened ASIC design system; radiation hardness tunable library cells; three company team; Application specific integrated circuits; Automatic control; Circuit synthesis; Libraries; Production; Radiation hardening; Silicon compiler; Silicon on insulator technology; Single event upset; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242943

Filename

242943