Title :
The Fault-Tolerant Design in Space Information Processing System Based on COTS
Author :
Fu, Jian ; Zhang, Chunyuan
Author_Institution :
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
In order to make Space Information Processing System (SIPS) based on Commercial-Off-The-Shelf (COTS) have a much stronger ability of radiation resistance in space, this paper presents multilevel fault-tolerant technique based on FPGA and Single Event Latch-up (SEL) resistance protection circuit. The multilevel fault-tolerant technique includes the dual fault-tolerant design on system level, the redundancy design of memory on module level and the fault-tolerant design of FPGA on chip level. By reliability analysis and experimentation, it can be concluded that the reliability of SIPS has been greatly increased by making use of fault-tolerant design. Moreover, this fault-tolerant design has been implemented successfully and run well.
Keywords :
fault tolerant computing; field programmable gate arrays; microprocessor chips; SEL resistance protection circuit; chip level design; commercial-off-the-shelf; field programmable gate array; memory design; multilevel fault tolerant technique; single event latch-up; space information processing system; system level design; Central Processing Unit; Circuits; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Information processing; Redundancy; Single event upset; Space technology; Switches; Space information processing system; commercial-off-the-shelf; fault-tolerant; single event latch-up; single event upset;
Conference_Titel :
Computer Science and Engineering, 2009. WCSE '09. Second International Workshop on
Conference_Location :
Qingdao
Print_ISBN :
978-0-7695-3881-5
DOI :
10.1109/WCSE.2009.877
